Digital-to-analog converters (DACs) produce an analog representation of a digital input code. The digital input code is typically directly input to a decoder which generates control signals to select a particular subset of a plurality of weighted analog elements that are summed to form an analog output. The configuration of weighted analog elements are commonly known as an analog network, since the analog network performs the function of converting digital control signals from the decoder into an analog output.
The analog elements of an electrical DAC is typically an electrical source such as a voltage or current source. Additionally, the analog elements of an electrical DAC may comprise a passive elements, such as resistors or capacitors configured as an analog network having an analog output that is an impedance. However, more generally a DAC includes a variety of control systems which convert a digital input code into an analog output. For example, a paint or ink color mixer that converts a digital input code into an analog colorant flow output is also a DAC. For example, the paint color mixer may have a plurality of electronically controlled valves coupling, in parallel, the colorant to a base paint. Each switchable valve may have a different maximum orifice size. A decoder may be used to select which of the valves is turned on as a function of the digital input code, thereby regulating the flow rate of a particular colorant added to the base paint. Generally speaking, a DAC may encompass any process or manufacturing method in which a digital input code may be converted into an analog output using a decoder and an analog network comprised of a plurality of switched analog network elements.
Although there are several different types of DAC, voltage converters are one of the most common types used to illustrate the general principles of DAC operation. The general principles of a DAC voltage converter are shown in FIGS. 1A-1C. In a DAC voltage converter, digital input codes are commonly converted to analog voltages by assigning a voltage weight, or a current weight, to each bit of the digital input code and summing the voltage or current weights of the entire code.
FIG. 1A shows a generalized DAC voltage converter 100, having a decoder logic 30, switches 20, analog network 40, reference source 10, and buffer amplifier 50. Decoder 30 receives a digital input code 5, typically in the form of a binary input word. The decoder 30, sometimes also called a control logic or a demultiplexer, selectively turns on and off switches 20 coupled to a analog network 40. Typically analog network 40 and decoder 30 are configured so that the analog output of analog network 40 is a linear function of the numeric value of a digital input code. However, the output of analog network 40 may also be a more complex mathematical function of a digital input code 5. Analog network 40 is commonly comprised of a resistor network in which a plurality of resistors are coupled to the network by switches 20 so that control signals from decoder 30 determine the output of analog network 40. However, analog network 40 may also be formed from a plurality of current or voltage sources. Analog network 40 is also sometimes called an analog output network, an attenuation network, or a decoding network. A reference source 10, typically a voltage source, is used so that the analog network 40 attenuates the reference source 10 according to an attenuation factor which is a function of the conductive state of switches 20. The output of the analog network 40 is typically coupled to a buffer amplifier 50. The analog output of the analog network 40 is typically plotted as a function of the digital input code, with the plot being described as the transfer function or the transfer characteristic of the DAC.
FIG. 1B is an illustrative prior art DAC voltage converter 110 with switches and resistors arranged in one common DAC voltage converter configuration. The analog network 40 and switches 20 are arranged as a parallel resistor network with each resistor connected by one switch between a reference voltage source 16 to the inverting node of an op-amp 18. Each subsequent resistor has twice the resistance of the previous resistor, thereby reducing its on-current by a factor of two. A five bit digital input code determines the switch positions of the five corresponding switches. The total current, I, of DAC 110 entering the inverting node of op-amp 18 is the sum of the binary weighted currents. The voltage, V.sub.out can be expressed as: V.sub.out =R.sub.f V.sub.ref (b.sub.1 /2R+b.sub.2 /4R+b.sub.3 /8R+b.sub.4 /16R+b.sub.5 /32R), where V.sub.ref is a reference voltage, R.sub.f is a feedback resistance 120, and b.sub.i is the i.sub.th bit value (zero or one). EQ. 1. This can also be expressed as: (R.sub.F /R V.sub.ref)B.sub.in, where B.sub.in =b.sub.1 2.sup.-1 +b.sub.2 2.sup.-2 +b.sub.3 2.sup.-3+b.sub.4 2.sup.-4 +b.sub.5 2.sup.-5. EQ.2.
There are several figures of merit to describe the response of a DAC. One limit to the response of DAC 110 is determined by the number of input bits. A large number of bits may permit a more accurate representation of an analog signal by allowing an analog signal to be represented with smaller step increments. The least significant bit (LSB) defines the smallest possible change in the analog output voltage. The LSB for a linear DAC is typically defined as: 1 LSB=V.sub.ref /2.sup.N, where V.sub.ref is the reference voltage and N is the number of bits. The resolution is typically described in terms of the increment of the least significant bit (LSB), which is the smallest analog signal increment which can be represented by the DAC. For a linear DAC with equal step heights (i.e., linear transfer function), the resolution, R, is given by the mathematical expression: R=1/[2.sup.N -1], where N is the number of bits. The greater the number of bits, the greater the potential resolution. However, the accuracy of a linear DAC is a function of other variables besides the number of bits. Absolute accuracy describes how close the output is to its ideal, or target value. Absolute accuracy depends upon the reference voltage and resistor tolerance. Relative accuracy refers to how close each output level is to its ideal fraction of full scale output. Relative accuracy depends principally upon on the tolerance of the weighted resistors. If the individual resistors of the analog network depart significantly from their target values the steps in the transfer function may be larger or smaller than 1 LSB. A monotonic DAC is one that produces an increase in output for each successive digital input. In order for a DAC to be monotonic the error, or differential non-linearity, must be less than .+-.1/2 LSB at each output level, which imposes tolerance requirements on the individual resistors comprising the analog network. The differential non-linearity, DNL, of a DAC is commonly expressed mathematically by: DNL.sub.n =the actual increment height of transition n--the ideal increment height. Generally, a DAC must have less than .+-.1/2 LSB of DNL if it is to be N-bit accurate. The dynamic range, DR, of a DAC is commonly defined as the ratio of the largrest output signal over the smallest output signal, and for a conventional DAC is related to the resolution of the converter by the equation: DR=20 Log(full scale/LSB) dB. Other common figures of merit for a DAC include the offset, gain error (ideal slope--actual slope), and integral nonlinearity.
A drawback of the DAC converter 110 shown in FIG. 1B is that it's unsuitable for achieving a large DR. This is because conventional manufacturing processes impose significant inter-lot and lot-to-lot fabrication variances on integrated circuit resistors. The actual tolerance of the resistors is a function of their target resistance values. The converter 110 of FIG. 1B requires that the largest resistor be 2.sup.N -1 times larger in value than the smallest resistor. As the number of bits increases to increase the DR, the range of resistor values increases correspondingly. However, in conventional integrated circuit manufacturing processes it is difficult to achieve a tight tolerance of each resistor while also increasing the range of resistor values, i.e., the process variation affects large value resistors differently than small value resistors. One conventional approach to the resistor tolerance problem is to use resistors with almost identical characteristics arranged in a slightly more complicated decoding network. FIG. 1C shows a DAC voltage converter 120 configuration which is commonly known as an R-2R ladder architecture. This configuration uses only two values of resistance in the ladder, R and 2R, and is preferred for DACs in which the output varies over several orders of magnitude. The ladder configuration results in a sequence of impedances in parallel at each subsequent node such that the ladder circuit results in a binary division of current. It can be shown that the output voltage of the R-2R DAC is of the form Vout=Vref(R.sub.F /R).SIGMA.b.sub.i /2.sup.i, where R.sub.f is the feedback resistance of op-amp 19, Vref is a reference voltage, and bi corresponding to the bit value (zero or one) of each switched 2R resistor of the ladder. EQ. 3. A chief advantage of the R-2R architecture is that the resistors can be fabricated with resistors having only two target values, which facilitates reducing the resistor variance, i.e., improving the tolerance compared to a configuration in which the resistor values vary over a wide range.
While the R- 2R architecture solves some of the fabrication problems of voltage converter DACs, the resistor ladder tends to occupy a large chip area when the ladder is scaled to achieve a large dynamic range. FIG. 1D is a schematic circuit diagram of a prior art programable resistor DAC 130 configured as a programmable logarithmic resistor. The analog network 40 and switches 20 are arranged as a parallel resistor network with each resistor connected by one switch to nodes R and S. Each subsequent resistor has 3.0769 decibels the resistance of the previous resistor, thereby reducing its on-current by a factor of 1.4251. A four bit digital input code determines the switch positions of the fifteen switches. FIG. 1D includes resistance values and a truth table for decoder 180. One advantage of the configuration of DAC 130 is that the value of each of the resistors increases such that a small total number of resistors may be used to select a programmable resistance over a large decibel range. However, a disadvantage of the embodiment of FIG. 1D is that it is difficult to achieve a high yield of DACs with desirable transfer characteristics. As can be seen in FIG. 1D, the target values of the resistors vary by up to a factor of seventy (i.e., from about 500 .OMEGA. to 35,000 .OMEGA.). It is very difficult to achieve a uniformly tight fabrication tolerance for resistors covering such a large range in values. The absolute value of each resistor will tend to have a significant variance from the target value (e.g., at least about 30%), depending upon the details of the fabrication process. Thus, while DAC 130 is compact, the yield of DACs having a transfer characteristic achieving desired figures of merit (e.g., absolute logarithmic linearity, logarithmic monotonicity, logarithmic dynamic range, etc.) tends to be undesirably low.
Routine fabrication variations in the resistors of a DAC voltage converter or programmable resistor may render the DAC unsuitable for its intended purpose. One way to compensate for fabrication variances in the resistance value of the resistors comprising a DAC is to mechanically trim the resistance values of the resistors comprising the DAC. In integrated circuits, individual resistor segments are sometimes trimmed using a laser beam to thin portions of a resistor by ablation (burning off) a portion of the resistor. However, trimming the resistors of an integrated circuit DAC with a laser beam can be an expensive and time consuming process because a large number of individual resistors must be trimmed at one time. It also requires a fabrication process consistent with laser ablation, i.e., fabricating metal segments designed to be thinned. Generally, conventional methods to trim the resistors of a DAC circuit increase the complexity and cost of fabricating a DAC circuit, particularly for compact integrated circuits.
One alternative to mechanically trimming the resistors of a DAC is to use a digital signal processor (DSP) to perform a calibration function. For example, a DSP may be used to performing a mapping function to compensate for a non-linearity in the transfer characteristic of a linear DAC. However, DSP circuits have limitations on the types of errors in target resistance values that they can trim. They require that a permanent memory be provided that can be programmed with extensive data on the transfer function along with signal processing circuits to perform a mapping function. Additionally, conventional DSP circuits tend to occupy a relatively large circuit area, which increases the cost of the integrated circuit. DSP circuits also consume significant amounts of power. The cost and complexity of integrating a DSP to perform a DAC trimming function is substantial. Consequently, in many applications, such as low voltage hearing aid circuits, it is impractical to use a DSP to compensate for manufacturing variations of the analog elements of the DAC.
While DAC voltage converters are one example of electronic circuits using analog networks, other electronic circuits and processes also use analog networks. Programmable resistors and programmable potentiometers are an important category of DAC. Programmable resistors and potentiometers typically use a network of resistors configured as an analog network in which a change in switch positions determines the output resistance of the analog network. Some of the individual resistors of the analog network may be out of tolerance, thereby degrading the performance of the programmable resistor. Additionally, systemic variations in lot-to-lot parameters of the resistor fabrication process may also result in a programmable resistor in which the resistance of all the resistors of the analog network are proportionately out of specification, thereby deleteriously effecting the ability of the programmable resistor to accurately convert a digital input code into the target analog resistance.
A variety of manufacturing processes also utilize switched weighted outputs configured in a manner analogous to the analog network of a digital to analog converter. The same generic problem is encountered in a variety of analog networks, namely that there is a manufacturing tolerance to the weighted analog outputs which limits the performance of the DAC.
What is desired is a new method and apparatus for reducing the effect of manufacturing variances in the weighted analog elements of an analog network on the performance of a digital to analog converter.